Recent developments in semiconductor processing technologies and memory cell technologies have continued to increase the density achieved in integrated circuit memory arrays. For example, certain passive element memory cell arrays, such as those including an antifuse cell, may be fabricated having word lines approaching the minimum feature size (F) and minimum feature spacing for the particular word line interconnect layer, and also having bit lines approaching the minimum feature width and minimum feature spacing for the particular bit line interconnect layer. Moreover, three-dimensional memory arrays having more than one plane or level of memory cells have been fabricated implementing such so-called 4F2 memory cells on each memory plane. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication,” and in U.S. Pat. No. 5,835,396 to Zhang, entitled “Three-Dimensional Read-Only Memory Array.”
A three-dimensional (3D) memory array is most efficient when the number of cell on each bit line and word line is large. This number of cells is frequently called the fan-out (N) of the bit line and the word line. A large fan-out reduces the number of vertical connections between the array lines on each memory layer and the circuitry below. These vertical connections cannot lie beneath the individual memory cells on each layer, and thus may add significantly to the chip area. But a large fan-out frequently has certain electrical disadvantages depending on the memory cell technology being used. For example, the capacitance of array lines and the resistance of array lines may increase by the fan-out (N) factor, and leakage per cell may cause power dissipation to increase by a factor of N2.
Another deleterious effect proportional to N2 is the reverse bias stress on unselected cells in a passive element memory array. In particular, unselected antifuse (AF) memory cells frequently have a large reverse bias during write conditions which can degrade the reliability of un-programmed cells if the voltage stress is maintained for a long period of time. The stress time on each cell is dependent upon the length of time that is necessary to write all the cells within a common group. For a two-dimensional (2D) array (i.e., having only a single memory plane) which is square, the common group of cells may be as large in number as the fan-out of the word line (N) times the fan-out of the bit line, or N2. For an integrated three-dimensional array of passive element memory cells that is fully mirrored, as many as three memory planes may be simultaneously biased in a group, so the stress time for an individual memory cell can be proportional to 3N2.
Reducing the fan-out breaks the array into many smaller sub-arrays or memory blocks and is less efficient in terms of support circuitry area versus memory cell area. As a result, 3D memory arrays must make a fan-out trade-off between electrical requirements and layout efficiency that is particularly detrimental in 3D passive element memory arrays.
Many two-dimensional memory arrays segment the memory array lines and connect the segments to longer lines. Examples include Flash EEPROM devices, which segment the bit lines, DRAMs (dynamic RAMs) which segment the word line and sometimes the bit line, and SRAMs (static RAMs) which segment the word line. Such devices have the segment switches on one layer (e.g., within the silicon substrate), and have a different layer of memory cells with segmented lines, and one layer of long lines (e.g., global lines). In FIG. 1, such a traditional segmented word line arrangement 100 is shown. A row decoder 102 generates a plurality of global word lines, such as global word line 103, which traverse across all or a portion of a memory array or sub-array. A segment select block 104 (which may be part of a column decoder circuit) generates a pair of segment select lines 105, 108 for coupling a selected one of segments 107, 110 through a respective device 106, 109 to the global word line 103. The global word lines, which run parallel to the word line segments, serve as bias lines to which a select word line segment is coupled.
Despite such progress, improved memory arrays having reduced leakage and stress time are desirable, particularly memory array configurations easily fashioned into a high density three-dimensional memory array.